JFETs are known to be desireable differential input pair transistors for opamps, compared with bipolar junction transistors (BJTs), because of their low input bias current and high AC performance. A known disadvantage of JFET inputs, compared with BJTs, is a high voltage noise (wherein voltage noise is measured in units of nanovolts (nV) per root Hertz (rtHz)).
JFET transistors are of two main types: P-channel (PJFET) and N-channel (NJFET). For illustrative purposes, a schematic symbol for a P-channel JFET 100 is shown in FIG. 1A. The P-channel of JFET 100, which consists of a semiconductor material which has been doped to contain an excess of holes, is between terminals 104 and 108. Of these two terminals, the terminal supplying the majority carrier of the channel (which is the more positive terminal for a P-channel device) is designated the source (S) while the other terminal is designated the drain (D). Between the source and drain of JFET 100's P-channel are two gates which are referred to as the top gate and the bottom gate. Each gate comprises a region of the P-channel which has been doped to contain an excess of electrons. The top gate is represented by terminal 102 while the bottom gate is represented by terminal 106.
The low input bias current of JFETs is due to the fact that, in normal operation, the gates control the flow of current between the source and drain by generating an electric field in the channel. This field is produced by applying a gate-to-source voltage between each gate and the channel which keeps the PN junctions reverse biased. The only current flow, and therefore the only input bias current, through the gates of a JFET during normal operation is due to leakage current.
For illustrative purposes, FIG. 1B depicts a known integrated circuit PJFET structure formed in a P-substrate 128. The P-channel 124 couples together terminals 114 and 118. The top gate is formed by terminal 112 and N.sup.+ region 122, while the bottom gate is formed by terminal 116, N.sup.+ region 120 and N region 126.
Desireable JFET characteristics may be utilized in opamps through known techniques of constructing the differential input pair from JFETs and coupling the respective inputs of the opamp to both the top gate and bottom gate of the corresponding differential input.
It would be desireable to further reduce the input bias current of a JFET opamp to provide circuit performance which approaches that of an ideal opamp requiring zero input bias current.
Typical techniques for reducing a JFET's input bias current (including the present invention) utilize the essential technique of decoupling the bottom gate of each JFET so that only the top gate is directly driven by the opamp's differential input. These techniques differ only in the means by which they drive the decoupled bottom gate. Directly driving only the top gate will also reduce the opamp's input capacitance. It is desireable to further reduce the input capacitance of an opamp because this approaches an ideal opamp which would have zero input capacitance. These reductions in input bias current and input capacitance are due, respectively, to the elimination of the bottom gate's leakage current and capacitance.
In typical integrated circuit JFETs the bottom gate's leakage current and capacitance are substantially higher than for the top gate. The differences in the physical structure of the top gate and bottom gate, which produce their differing electrical characteristics, are also illustrated by FIG. 1B. The N.sup.+ region 122, which forms the top gate, is substantially smaller than N region 126 which forms the bottom gate. Directly driving only the top gate 122 will substantially lower the input bias current (typically by about one order of magnitude) since the PN junction between top gate 122 and P-channel 124 is substantially smaller than the PN junction between bottom gate 126 and P-channel 124. In addition, directly driving only the top gate will substantially reduce the input capacitance since the capacitance of top gate 122 is substantially smaller than the capacitance of bottom gate 126.
The circuit which drives the bottom gate must track the voltage of the top gate to prevent a problem with JFETs known as "punch through." Punch through, which is defined as conduction produced by a breakdown between the top gate and bottom gate, occurs when the top gate's voltage differs from the bottom gate's voltage by a relatively small amount (typically 4 to 5 volts) causing the normally reverse biased PN junctions between the top gate and bottom gate to break down. This problem cannot be solved by tying the bottom gate to a fixed voltage because this would severely limit the input voltage range of the opamp.
One known technique for driving the bottom gate, for each differential JFET input of an opamp, is to have a voltage follower circuit connected between each opamp input and the bottom gate of its differential input JFET. The voltage followers address punch through by keeping each bottom gate voltage the same as its corresponding top gate voltage. However, the addition of voltage follower circuits introduce several deficiencies. First, punch through can still occur if the slew rate of either follower circuit is exceeded. Secondly, the follower circuits add their own input bias currents to that of the JFET. Thirdly, the follower circuits add their own power requirements to those of the opamp. Finally, the follower circuits require significant additional circuitry thereby increasing die size and reducing reliability.
In view of the foregoing, it would be desirable to provide an improved circuit for driving the bottom gate of a JFET.
It would also be desirable to limit the extent to which a punch through current, through one of the opamp's inputs, effects the signal source driving the other input opamp input.